||Xuan Guan, Assistant Professor
Dept. of Computer Engineering
College of Engineering
San Jose State University, USA
|  Research Interests
|  Return to List
She received her Ph.D. in Computer Engineering from University of Connecticut in 2011. Her research interest spans in the general area of computer architecture and embedded systems, with specific focus on reconfigurable and energy efficient processor design, mobile computing, automotive microcontroller and secure computer architecture. Before joining San Jose State University in September 2016, she worked as an IC design engineer in NXP Semiconductor Inc. from 2011 to 2016. She has participated in the development of 3 multi-million gates microcontroller processors, which have been widely used in automotive and IoT applications.
(1) Design Engineer, NXP Semiconductor Inc, Austin, TX, USA 01/2011 to 08/2016.
SELECTED RECENT PUBLICATIONS:
1. Xuan Guan and Yunsi Fei, “Hierarchical Design of an Application-specific Instruction Set Processor for High-throughput and Scalable FFT Processing” IEEE Trans. on VLSI, vol. 20, no. 3, pp. 551 - 563, Feb. 2011.
2. Xuan Guan and Yunsi Fei, “Register file partitioning and compiler support for reducing power consumption in embedded processors,” IEEE Trans. on VLSI, vol. 18, no. 8, pp. 1248 - 1252, Aug. 2010.
3. Xuan Guan and Yunsi Fei, “Register file partitioning and re-compilation for register file power reduction,” ACM Trans. on Design Automation of Electronic Systems, vol. 15, no. 3, May 2010.
4. Xuan Guan and X. H. Ba and R. Z. Mu and Y. Q. Cheng and J. Chen “Novel Adaptive Threshold Setting Algorithm for GPS Receiver” Chinese Journal of Electron Devices, vol. 30, no. 2, 2007
5. Hai Lin and Yunsi Fei and Xuan Guan and Z. J. Shi “Architectural Enhancement and System Software Support for Program Code Integrity Monitoring in Application-Specific Instruction-Set Processors” IEEE Trans. on VLSI, Vol. 18 , Issue 11 , pp. 1519, Nov. 2010
6. Xuan Guan and Yunsi Fei, “Adaptive extended min-sum algorithm for nonbinary LDPC decoding,” Proc. IEEE GLOBECOM, Dec. 2011.
7. Xuan Guan, Yunsi Fei, and Hai Lin, “A hierarchical design of application-specific instruction set processors for high-throughput FFT,” in Proc. IEEE Int. Symp. on Circuits and Systems, May 2009
8. Xuan Guan, Hai Lin, and Y.Fei, “Design of an application-specific instruction set processor for high-throughput and scalable FFT,” in Proc. IEEE Design Automation & Test in Europe Conf., Apr. 2009.
9. Xuan Guan and Yunsi Fei, “Reducing power consumption of embedded processors through register file partitioning and compiler support,” in IEEE Int. Conf. ASAP, July 2008.
10. Hai Lin, Xuan Guan, Yunsi Fei, and Z. Shi, “Compiler-assisted architectural support for program code integrity monitoring in application-specific instruction set processors,” in IEEE International Conference on Computer Design (ICCD), Oct. 2007
11. Yunsi Fei, Hai D. Lin, and Xuan Guan, “A hardware/software cooperative approach for reducing memory traffic in application-specific instruction set processors,” in IEEE Int. Midwest Symp. on Circuits & Systems, Aug. 2007.